1. Field of the Invention
The present invention relates to semiconductor devices, and in particular, to interconnecting a semiconductor die to a terminal lead in a semiconductor package.
2. Related Art
In the manufacture of semiconductor devices, active elements in a semiconductor device, such as drain and/or source regions in a semiconductor die, are electrically connected to other devices or electronic components, such as on a printed circuit board. However, since semiconductor devices can be susceptible to environmental conditions, such as dust, moisture, and sudden impact, which can damage or otherwise interfere with the proper operation of the device, the device is typically protected by a die package. The die package both protects the die and allows the die to electrically connect to external devices. To facilitate the latter, specific portions of the die are electrically coupled to external leads of the package or lead frame, such as with bond wires or solder balls.
FIG. 1 shows a side view of a typical connection between a power semiconductor die 10 (e.g., a MOSFET) and part of a lead frame 12. Lead frame 12 includes a lead 14 and a die pad 16. Lead 14 allows die 10 to electrically couple external elements after die 10 is connected. Die 10 is mounted on or secured to die pad 16. The upper surface of die 10 includes a metalized portion 22, such as aluminum, that provides contact with underlying active elements of die 10. An electrical connection is then made between metalized portion 22 and contact portion 18. Typically, the connection is made by bonding, e.g. ultrasonically bonding, a conductive wire 24 between the two portions. Materials for wire 24 include gold, aluminum, and copper. FIG. 1 shows a single bond, connection, or stitch 26 between wire 24 and metalized portion 22.
The amount of current flow from die 10 to lead 14 depends, in part, on the total resistance in the current path, as shown by the arrows in FIG. 1. This resistance is due, in part, to the resistance of wire 24 and the spreading resistance along metalized portion 22. The spreading resistance increases as the distance the current has to travel from the metalized portion to the stitch increases. The spreading resistance also increases as the thickness of metalized portion 22 decreases. Typical metalization thickness is in the range of approximately 3 to 5 microns (i.e., much smaller than the wire thickness). It is desirable to lower the overall electrical resistance of the connections, especially to keep pace with the intrinsic resistance of the semiconductor die, which is continuously decreasing. However, increasing the thickness of metalized portion 22 also increases the cost by decreasing throughput of the wafer/die manufacturing process.
Further, wires are limited by their size, typically around 20 mil in diameter, which also limits the amount of current that can be carried in each wire. Consequently, large numbers of wires are sometimes needed to make the desired connections in certain applications, which can increase the cost and decrease throughput of the interconnect process equipment (e.g., the wire bonder).
Instead of wires, other types of bonding utilize a strap to connect the die to the lead frame. One such configuration is shown in FIG. 2 and is disclosed in U.S. Pat. No. 6,040,626, entitled “Semiconductor Package”, issued to Cheah et al. A single conductive strap 50, e.g., copper, is used to obtain an electrical connection between metalized portion 22 on die 10 and lead 14 of the package/module. Strap 50 can be either soldered or glued to two contact areas 52 and 54, such as with an electrically conductive epoxy or solder paste 56. Use of a strap provides the advantages of reducing resistance to current flow by providing a large contact area for coupling metalized portion 22 to lead 14, e.g., spreading resistance is greatly reduced.
However, using a strap also has disadvantages. In order to solder strap 50 to the surface of metalized portion 22, a solderable metalization, e.g., copper or nickel, is required. In general, such a metalization requires a stack of several different metal layers (not shown), with each layer having a specific function, e.g., adhesion, barrier, and solderability, of the soldering process. These layers, which are different than the standard metalization layer, e.g., aluminum, together result in higher manufacturing cost of the metalization, and consequently of the semiconductor die. Typically, a solder paste process is applied to join the parts. Solder paste 56 contains some type of flux component, which is required to (1) temporarily tack the components, (2) protect them from oxidizing (especially if the reflow process takes place in air), and (3) remove/reduce oxides already present. Depending on the quality of the parts, only the use of a strong flux provides a robust process and reliable result of the soldering process. It is well known that flux residues cover the surfaces after reflow. Beside other negative effects (like corrosion in contact with humidity), their presence negatively influences the strength and reproducibility of the adhesion of the molding compound in a subsequent package encapsulation. This again can result in a limited reliability of such parts. As a consequence, parts processed with solder paste typically need to be thoroughly cleaned after reflow and before further processing/packaging.
However, cost effective wet chemical cleaning processes are known to offer limited process control capability, causing an increased yield loss potential, beside the additional costs (e.g., labor, floor space, equipment, consumables, and yield loss) due to the need for this additional process step. Such a cleaning is also difficult to automate (which would reduce labor cost) and difficult to implement in a clean room environment. Furthermore, wet chemical processes, as well as solder reflow using flux (fumes), may be environmentally unfriendly. Two other disadvantages of a copper strap interconnect are (1) limited flexibility (since the straps are typically stamped on the die bonder, device changes which require a different strap geometry will require exchanging the stamping tool, which increases time and cost) and (2) the relatively stiff copper strap can form a significant stress on the silicon die, which can cause the die to crack, especially if the thickness of the attachment layer (e.g., solder or epoxy) is not well controlled above a certain minimum.
Another type of interconnect currently used is a solder ball based interconnect, such as disclosed in U.S. Pat. No. 6,442,033, entitled “Low-cost 3D Flip-chip packaging technology for integrated power electronics modules”, issued to Liu Xingsheng et al., and in U.S. Pat. application publication No. US 2002/0066950, entitled “Flip chip in leaded molded package with two dice”, by Rajeev Joshi, both of which are incorporated by reference in their entirety. Solder ball based interconnects have similar disadvantages to those of the strap configuration with regards to the use of solder paste and inflexibility. In high current applications, such a configuration has the additional disadvantage of the solder's high susceptibility to electromigration.
Thus, it is highly desirable to use a clean, environmentally friendly process, which can be well controlled, as well as a flexible interconnect. The ultrasonic bonding process is one such process. However, it is also desirable to reduce the number of connections, in order to increase the production rate of existing equipment, and reduce the cost of manufacturing. Furthermore, it is desirable to improve the electrical performance of connections, which would require either reducing the electrical resistance and/or increasing the current capability, depending on the type of application. Especially for discrete semiconductor devices, it is also desirable to reduce the overall size of a device, and therefore the volume required by the connection.
Accordingly, there is a need for an improved type of connection processed using ultrasonic bonding, which overcomes the deficiencies in the prior art as discussed above.